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Table 1. Pin Description
Pin #
1
2
3
4
5
Pin Name
VDDIO
BYP
NC
SCL
GND
Description
Internal Power Supply (1.62V - 3.6V)
Bypass capacitor (0.1 μ F)
Leave open. Do not connect
I 2 C Serial Clock
Connect to Ground
Pin Status
Input
Input
Open
Open Drain
Input
6
SDA
I 2
C Serial Data
Open Drain
7
8
9
10
11
12
13
14
15
16
SA0
NC
INT2
GND
INT1
GND
NC
VDD
NC
NC
I 2 C Least Significant Bit of the Device I 2 C Address
Internally not connected (can be GND or VDD)
Inertial Interrupt 2
Connect to Ground
Inertial Interrupt 1
Connect to Ground
Internally not connected (can be GND or VDD)
Power Supply (1.95V to 3.6V)
Internally not connected (can be GND or VDD)
Internally not connected (can be GND or VDD)
Input
Input
Output
Input
Output
Input
Input
Input
Input
Input
The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic plus 4.7 μF bulk, or a
single 4.7 μF ceramic) should be placed as near as possible to the pins 1 and 14 of the device.
The control signals SCL, SDA, and SA0 are not tolerant of voltages more than VDDIO + 0.3V. If VDDIO is removed, the control
signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) are user programmable through the I 2 C
interface. The SDA and SCL I 2 C connections are open drain and therefore require a pullup resistor as shown in the application
diagram in Figure 4 .
1.1
Soldering Information
The QFN package is compliant with the RoHS standard. Please refer to AN4077.
MMA8451Q
Sensors
Freescale Semiconductor, Inc.
5
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